High Speed Downlink Packet Access (HSDPA) is a packet based data service feature of the in WCDMA standard providing high speed downlink transmission. HSDPA is a technology upgrade to current UMTS networks.
In Release 7 3GPP Standard, Multiple Input Multiple Output (MIMO) HSDPA is supported to double the nominal achievable data rate.
Compared to SISO/SIMO case (rel. 6 and previous), the HSDPA receiver must support improve to perform time and spatial equalization.
MIMO has significant impact on the UE receiver algorithms & complexity                baseline receiver is linear Mean Minimum Squared Equalizer (MMSE) w/o interference cancellation        enhanced receiver would be nonlinear with different options for interference cancellation        
Some techniques are known in the prior art in order to provide such time and spatial equalization.
A first known technique is illustrated in FIG. 1 which shows a MIMO HSDPA receiver which includes a joint time-spatial LMMSE chip level equalizer 10 providing both temporal and spatial equalization of the two received streams. Furthermore, equalization 10 achieves the decoding of the Dual Transmission Adaptive Array (DTx-AA) standard.
Once equalized, the two received streams are separately processed in parallel.
A first processing path includes a dispreading block 11, a Log Likehood Computation Ratio (LLR) Comp. block 12, a Rx HARQ block 13 and a decoding block 14. Dispreading block 11 achieves downsampling of the received chip level sequence in order to generate the sequence of symbols. Rx HARQ block 13 handles the packet retransmission procedure defined in the above mentioned 3GGP standard while decoding block 14 embodies known channel decoding technique, such as based on turbo-codes.
Similarly, the second stream outputted by joint time/spatial equalizer is processed by a dispreading block 15, a Log Likehood Computation Ratio (LLR) block 16, a Rx HARQ block 17 before being decoded by a decoding block 18.
The first technique shown in FIG. 1 suffers one main drawback consisting in the high complexity of the joint time-spatial LMMMSE which has to provide effective time and spatial equalization. Such block is rather complex to embody, and particularly because it has to operated at the chip level frequency.
Other techniques are known which are based on a Serial Interference Cancellation (SIC) arrangement.
FIG. 2 shows one second known technique—also known under the designation V-blast—which is based on such a SIC structure comprising a 2×1 MMSE equalization block 20 which only provides joint time-spatial equalization of one particular stream complying with one criterium such as, for instance, the power. Such stream is then processed by one single path comprising, similarly as in the first technique, a dispreading block 21, a Log Likehood Ratio (LLR) block 22, a Rx HARQ block 23 and a decoding block 24.
FIG. 2 also shows that a cancellation loop is arranged between the output of LLR block 22 and the input of 2×1 MMSE equalizer block, comprising a hard decision block 26, a signal reconstruction block 25 comprising estimation of the channel and having the purpose of re-generating the chip level sequence corresponding to the first signal.
Thanks to that cancellation loop, the chip level sequence corresponding to the signal received from the first antenna can be suppressed before being reprocessed by equalizing block 20 for the purpose of decoding the second signal.
A second type (type 2) of a SIC is further illustrated in FIG. 3 which differs from the second known technique in that the cancellation loop is connected at the output of the decoding block.
FIG. 3 illustrates such a SIC receiver of the second type which includes a 2×1 MMSE equalization block 30 providing temporal and spatial equalization of the higher power received signal, then following by a dispreading block 31, a Log Likehood Ratio (LLR) block 32, a Rx HARQ block 33 and a decoding block 34. Once the higher level signal has been decoded, the latter is re-encoded by encoder 37, then forwarded to a Tx-HARQ block 36 managing the transmission of packets, and then processed by a signal reconstruction block 35 which regenerate, taking into account the channels characteristics estimation, the chip level sequence corresponding to the first signal.
As shown in the FIG. 2, the cancellation loop regenerates the chip level sequence corresponding to the first signal which can then be suppressed from the signal of the corresponding antenna so as the equalizing block 30 may equalize, process and decode the second signal.
That first known technique, based on the SCI (type 2), shows higher complexity and latency than the SIC of the first type. Conversely, it provides higher performance.
However the two SIC structures which are illustrated in FIGS. 2 and 3, respectively, requires additional storage for successively storing the sequence of data being processed before the whole 2-step-equalization completes. In addition, it should be noticed that 2×1 MMSE equalizers 20 and 30, although being of less complexity than the linear 2×2 MMSE equalizer of FIG. 1, have to operated a at frequency being double than the chip level rate.
The need of additional storage and the increase in the frequency of operation of equalizers 20 and 30 finally also results in an increase of the manufacturing costs of the MIMO receiver.
Therefore, there is a desire for a new architecture of a MIMO receiver which, firstly, can be based on an equalization technique of reasonable complexity and, secondly, does not need additional storage for storing two successively processed streams of data.